This invention relates generally to semiconductor devices and manufacturing methods and more particularly to field effect semiconductor devices and manufacturing methods.
As is known in the art, metal gate and junction gate field effect transistors, sometimes referred to as MESFET and JFET devices, have been formed on high resistivity silicon, gallium arsenide, or silicon on sapphire substrates. In order to achieve efficient operation at microwave frequencies in excess of 1 GHz the gate length should be 1 micrometer or less, the gate capacitance should be small, the depth of the conducting channel should be substantially smaller than the length of the gate in order to avoid increasing the effective conductive channel length of the device because of fringing fields, the conductive channel doping should be relatively high, (e.g., N=10.sup.17 atoms/cm.sup.3), the carrier mobility in the conductive channel region should be high to achieve a low on-resistance of the device, the source-drain spacing should be small (e.g. less or equal to 3 micrometers), the contact impedance should be small, and the gate leakage current should be small in order to avoid excessive loading of a drive circuit.
While the requirement of a very shallow conductive channel depth of 0.2 to 0.3 micrometers may be met using gallium arsenide material by forming an appropriately doped, shallow epitaxial layer on an insulating gallium arsenide substrate, and using silicon by an epitaxial or ion implanted layer on a highly resistive single crystal silicon substrate, meeting such shallow channel depth requirement is difficult where the epitaxial layer is of one material, such as silicon, and the substrate is of a different material such as sapphire. That is, complications arise in forming very shallow conductive channel depths for MESFET or JFET devices using silicon on sapphire substrates because of the fact that the electrical properties of the silicon film on the sapphire substrate are generally poor at and near the silicon-sapphire interface. Consequently, while silicon on sapphire devices are theoretically highly desirable since they have greatly reduced parasitic capacitances and readily lend themselves to the fabrication of microwave monolithic integrated circuits, when such devices utilize the full thickness of the silicon the minimum thickness of the silicon, and hence the minimum thickness of the channel depth, is typically 6000 .ANG. and therefore the depth of such conductive channel is only slightly shorter than the gate length. However, if the conductive channel depth is only slightly shorter than the gate length fringing fields spread, increase the effective gate length of the device, and thereby reduce the operating frequency bandwidth of the device.
As is also known in the art, devices of the type described above are generally made by positioning a gate, 1 micrometer or less in width, with a very high degree of masking accuracy precisely between the source and drain regions, which are typically spaced 3 micrometers apart. This is a particularly difficult task, especially if the device is shaped so that registration in two dimensions must be achieved, e.g. in an interdigitated structure. Such technique is usually a so-called "lift-off" technique where a layer of photoresist is deposited on the surface of the semiconductor and patterned to expose the gate of the semiconductor region. Metal is then deposited over the photoresist and onto the exposed gate region. The photoresist with metal on its surface is then lifted off to leave the metal gate on the semiconductor. Such technique may be useful in some applications. However in those applications where it is desired to form a Schottky contact using a platinum deposition and a high temperature process to form platinum-silicide prior to deposition of an aluminum metal gate contact, the photoresist is not generally capable of withstanding such high temperature process thereby limiting the use of this "lift-off" technique.